Design and Analysis for 3D Vertical Resistive Random Access Memory Structures with Silicon Bottom Electrodes

  • Kim, Tae-Hyeon; 
  • Kim, Sungjun; 
  • Kim, Min-Hwi; 
  • Cho, Seongjae; 
  • Park, Byung-Gook
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초록

In this work, we propose two 3D vertical RRAM structures and their detailed fabrication methods. One is a double-horizontal-electrode (DHE) structure where a top electrode covers both sides of a silicon bottom electrode, and the other is a gate-all-around (GAA) structure where silicon nanowires are enclosed by resistive switching layers and resistive switching layers are enclosed by top electrodes. In these two 3D vertical structures, the chemical vapor deposition (CVD) process is essential for deposition of a resistive switching layer and a top electrode material, and heavily doped silicon should be applied as a bottom electrode. Several advantages of resistive random access memory (RRAM) with metal-insulator-semiconductor (MIS) structure are also investigated. Furthermore, we fabricated a W/Si3N4/n+-doped-polysilicon RRAM device, composed of suitable materials for the proposed 3D RRAM structures and investigated its resistive switching characteristics.

키워드

3D Vertical Structure; Si3N4 Based RRAM; Resistive Switching; LOW-POWER
제목
Design and Analysis for 3D Vertical Resistive Random Access Memory Structures with Silicon Bottom Electrodes
저자
Kim, Tae-Hyeon; Kim, Sungjun; Kim, Min-Hwi; Cho, Seongjae; Park, Byung-Gook
DOI
10.1166/jnn.2017.14760
발행일
2017-10
유형
Article
저널명
Journal of Nanoscience and Nanotechnology
권
17
호
10
페이지
7160 ~ 7163