Quantitative analysis of positive-bias-stress-induced electron trapping in the gate insulator in the self-aligned top gate coplanar indium–gallium–zinc oxide thin-film transistors

초록

We experimentally extracted the positive bias temperature stress (PBTS)-induced trapped electron distribution within the gate dielectric in self-aligned top-gate (SA-TG) coplanar indium– gallium–zinc oxide (IGZO) thin-film transistors (TFTs) using the analytical threshold voltage shift model. First, we carefully examined the effects of PBTS on the subgap density of states in IGZO TFTs to exclude the effects of defect creation on the threshold voltage shift due to PBTS. We assumed that the accumulated electrons were injected into the gate dielectric trap states near the interface through trap-assisted tunneling and were consequently moved to the trap states, which were lo-cated further away from the interface, through the Poole–Frenkel effect. Accordingly, we quantita-tively analyzed the PBTS-induced electron trapping. The experimental results showed that, in the fabricated IGZO TFTs, the electrons were trapped in the shallow and deep trap states simultane-ously owing to PBTS. Electrons trapped in the shallow state were easily detrapped after PBTS ter-mination; however, those trapped in the deep state were not. We successfully extracted the PBTS-induced trapped electron data within the gate dielectric in the fabricated SA-TG coplanar IGZO TFTs by using the proposed method. © 2021 by the authors. Licensee MDPI, Basel, Switzerland.

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