ScholarWorks@중앙대학교

초록

Most previous studies have modeled resistive switching based on physical principles. While physics-driven models provide valuable physical insight, their complexity and device specificity limit scalability and often result in high computational costs in large-scale circuit simulations. To address these limitations, we propose a generic compact modeling methodology in LTspice. This generalized approach constructs compact models for diverse resistive memory technologies using a minimal set of common circuit elements. It integrates nonlinear resistors, capacitors, and switches to reproduce key switching phenomena—including filament formation, polarization-modulated tunneling, and spin-dependent resistance—thereby capturing the essential behaviors of RRAM, TS, FTJ, and MRAM. This generalized framework enables flexible parameter tuning to reflect each device’s distinct switching dynamics. Validation using experimental and reference data confirms that the resulting models accurately reproduce the key switching characteristics across all four device classes. Monte Carlo simulations further demonstrate the framework’s ability to capture variability arising from parameter fluctuations and cycling effects. The proposed framework scales seamlessly from single-device operation to array-level simulation, enabling performance evaluation of SNN- and BNN-based inference systems and supporting accurate estimation of power consumption. Collectively, these results demonstrate the framework’s broad applicability and scalability for large-scale neuromorphic and in-memory computing architectures.

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