ScholarWorks@중앙대학교

초록

Charge domain SRAM-based Process-In-Memory (PIM) has been tremendously researched for recent years to improve throughput and energy efficiency in data intensive neural network applications. However, there are two main issues that need to be resolved in charge domain SRAM-based PIM architectures, 1) minimizing area overhead while supporting multi bit Multiply-and-Accumulate (MAC) operation, 2) addressing the MAC operation gain error and offset error due to PVT-varied input Digital-to-Analog data Converters (DACs) and in-array coupling noises, respectively.In this work we presented novel charge coupling based coupled 7T 1C SRAM PIM architecture with gain/offset error auto-compensated SAR ADC which gives solutions to these two issues. Proposed coupled 7T 1C SRAM bitcell structure is only 7 percent bigger than conventional 6T SRAM bitcell, which gives high benefit in terms of area efficiency. Furthermore, to remove the gain error and offset error, we developed gain/offset error auto-compensated SAR ADC. Proposed gain/offset error auto-compensation technique prevents the worst case accuracy drop of 40.57 percent for CIFAR-10 dataset classification and 24.93 percent for CIFAR-100 dataset classification when considering ff/1.1V/cold and ss/0.9V/hot PVT conditions, respectively. © 2024 Copyright is held by the owner/author(s). Publication rights licensed to ACM.

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