A framework for non-contact wafer level testing of wireless NoC-based SoCs

초록

Computational power and customers’ demand of sophisticated devices are evolving complex systems integrated into a chip. Recently, wireless network-on-chip (WiNoC) is developed as an on-chip interconnect for complex integrated circuits (ICs) to resolve the issues of latency, power consumption, throughput etc. The post-fabrication testing of such complex ICs is also a challenging job, especially in order to perform direct contact testing of wafer level VLSI chips. One of the reasons is the increasing density of contact pads that has direct impact from the increasing complexity of ICs. This paper presents a framework for non-contact wafer-level testing of WiNoC-based system-on-chip, while reusing on-chip communication infrastructure. It is scalable with respect to the technological advancements and offers significant advantages over conventional direct-contact and non-contact testing methods. © Research India Publications.

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