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A 20-Gb/s Half-Rate PAM-4 Receiver With Time-Based FIR-IIR DFE
- Seong, Kiho;
- Baek, Kwang-Hyun;
- Kim, Tony Tae-Hyoung
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0초록
This paper presents a four-level pulse amplitude modulation (PAM-4) receiver employing a time-based finite impulse response (FIR) and infinite impulse response (IIR) decision feedback equalizer (DFE). A linearity-enhanced inverter-chain delay line is proposed to improve the linearity of the time-domain IIR DFE. The PAM-4 signal decoding and DFE operations are implemented entirely in the digital domain, consuming only 2.39 mW in a 65-nm CMOS process and achieving an energy efficiency of 0.12 pJ/bit at a 20-Gb/s data rate.
키워드
Four-level pulse amplitude modulation; PAM-4; infinite impulse response decision feedback equalizer; IIR-DFE; time-domain receiver
- 제목
- A 20-Gb/s Half-Rate PAM-4 Receiver With Time-Based FIR-IIR DFE
- 저자
- Seong, Kiho; Baek, Kwang-Hyun; Kim, Tony Tae-Hyoung
- 발행일
- 2025-07
- 유형
- Conference Paper
- 저널명
- 2025 International Technical Conference on Circuits/Systems, Computers, and Communications, ITC-CSCC 2025