Effect of planarity on the 3D integration in 3-D integrated CMOS image sensor

초록

The back illuminated image sensor is quickly advancing as a solution to some of the problems that limit imager performance as pixel sizes decrease. Several examples of back illuminated sensors have been demonstrated in previous publications and the first announcements of mass produced BSI sensors were recently made by major sensor companies[1-5]. Along with the inherent optical advantages of back illumination, including the ability to capitalize on lower f# lenses, there are challenges that arise from implementing BSI architectures in high volume in a cost effective manner. CMOS image sensor have a light receiving element, a digital control block, and a peripheral circuit such as an analog-to-digital converter are arranged at a limited area within a chip. Because an area ratio of a pixel array per a chip area is limited, an amount of light that one light receiving element can collect is reduced and noise is increased, causing various problems such as image loss. Complex 3-D integration structures have many technologically relevant applications such as decreasing optical crosstalk in CMOS image sensor. Back-illuminated imaging is receiving an increasing interest as a solution to some of the problems that limit imager performance as pixel size decreases. The amount of available light per pixel decreases as pixel size decrease. Optical advantages of back illumination (BSI) can be decreased in pixel sizes continually and driven by system cost, die size. It can be increased in picture resolution and total camera module size. The dense vertical interconnection of multiple circuit layers have been developed using a three-dimensional(3D) circuit integration technology including wafer bonding, wafer thinning, deep Si etching process. © 2011 IEEE.

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