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Design and implementation of an enhanced anti-SAT framework for robust protection against SAT-based attacks on logic-locked circuits
- S, Kamatchi;
- Priya, A. Swetha;
- Prasad, E.L.;
- Rani, M. Thillai;
- Pranav, V. Sri;
- ... Kang, Dong-Won;
- 외 1명
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1초록
Ensuring the security of Integrated Circuits (ICs) against reverse engineering and unauthorized access is challenging. They are vulnerable to Satisfiability (SAT)-based attacks, which can systematically reduce the search space by effectively bypassing conventional logic locking techniques. The existing methods are vulnerable to skew in the algorithms or signal probability skew-based removal attacks or takes required overhead. To fill this gap, we propose a new compact lightweight Anti-SAT block (ASB) and its obfuscation approach together with a Challenge-Response Authentication Framework (CRAF) that exponentially increases IC security by making SAT solver complexity infeasible to attackers through decoy keys. The Anti-SAT Block (ASB) includes decoy keys which exponentially increase the complexity of SAT solver, and from which true keys cannot be recovered. Incorporation of ASB in a locked circuit thwarts vulnerable SAT attacks. The novelty is that the proposed ASB design with obfuscation technique not only provides effective protection against SAT attacks but also provides ATPG-based cost-effective secured locking mechanism with reduced overhead. The challenge-response module also assures that access is valid, by authenticating it and preventing the circuit from being opened by unauthorized users. The proposed novelty achieves a high fault detection efficiency of 98% and test pattern coverage of 99% with very low power down to 48% and area overhead of 12% which is suitable for high-security applications. This solution provides superior resistance to SAT-based attacks that provide resistance over the traditional key gate-based logic locking techniques and protect sensitive ICs from advanced hardware threats. This work demonstrates the strength of the Anti-SAT and authentication framework in protecting modern IC designs and provides promise as a solution for critical applications in defense, finance, and other security-sensitive industries. © 2025 The Author(s)
키워드
- 제목
- Design and implementation of an enhanced anti-SAT framework for robust protection against SAT-based attacks on logic-locked circuits
- 저자
- S, Kamatchi; Priya, A. Swetha; Prasad, E.L.; Rani, M. Thillai; Pranav, V. Sri; Bahadur, Jitendra; Kang, Dong-Won
- 발행일
- 2025-09
- 유형
- Article
- 저널명
- Results in Engineering
- 권
- 27
- 언어
- ENG
- 출판사
- Elsevier B.V.
- 발행국가
- 네덜란드
- ISSN
- E 2590-1230
P 2590-1230