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Effect of ashing conditions and optimization of nano process integration in copper/porous low-k nano-interconnects
- Pyo, S.G.;
- Kim, S.W.
WEB OF SCIENCE
3SCOPUS
3초록
We report the optimization of ashing conditions and the process integration of a chemical vapor deposition (CVD) ultra low-k (k =2.2) organosilicate (OSG) dielectric in a top hard mask damascene structure. The N2/H 2 ash showed the lowest resistance-capacitance (RC) product and a dual top hard mask approach for dual damascene processing was built, using 200 nm SiC/50 nm SiO2 as the hard mask. This CVD low-k material had no low-k voiding, unlike other spin-on dielectric (SOD) low-k materials. The presence of the densified layer around the trench during the ashing process could improve the precursor penetration during the CVD barrier metal deposition process. Copyright © 2012 American Scientific Publishers.
키워드
- 제목
- Effect of ashing conditions and optimization of nano process integration in copper/porous low-k nano-interconnects
- 저자
- Pyo, S.G.; Kim, S.W.
- 발행일
- 2012-11
- 유형
- Article
- 권
- 12
- 호
- 11
- 페이지
- 8401 ~ 8406
- 언어
- ENG
- 출판사
- American Scientific Publishers
- 발행국가
- 미국
- 분량
- 6 페이지
- ISSN
- E 1533-4899
P 1533-4880