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A 10-bit, 50 MS/s, 55 fJ/conversion-step SAR ADC with split capacitor array
- Cho, S.-J.;
- Hong, Y.;
- Yoo, T.;
- Baek, K.-H.
Citations
SCOPUS
3초록
In this paper, a split capacitor array structure for successive approximation register (SAR) ADC is proposed. By connecting the node of upper plate of LSB capacitor arrays to the reference voltage while MSB operation is activated, the proposed ADC can alleviate the problem of parasitic capacitance without using extra calibration circuitry and conversion cycles. The proposed ADC is designed using 0.13-um 1P6M CMOS technology. At a 1.2-V supply and 50 MS/s, the ADC achieves an SNDR of 56.9 dB and consumes 1.58 mW, resulting in a figure of merit (FOM) of 55 fJ/conversion-step. The ADC core occupies an active area of 350 × 440 um 2.
키워드
Analog-to-digital converter (ADC); attenuation capacitor; split capacitor array; successive approximation register (SAR); Active area; Analog to digital converters; Capacitor arrays; CMOS technology; Conversion cycles; Figure of merits; Parasitic capacitance; Reference voltages; SAR ADC; Split-capacitor arrays; Successive approximation register; Upper plate; Approximation theory; CMOS integrated circuits; Capacitors
- 제목
- A 10-bit, 50 MS/s, 55 fJ/conversion-step SAR ADC with split capacitor array
- 저자
- Cho, S.-J.; Hong, Y.; Yoo, T.; Baek, K.-H.
- 발행일
- 2011-10
- 유형
- Conference Paper
- 저널명
- Proceedings of International Conference on ASIC
- 페이지
- 472 ~ 475
- 언어
- ENG
- 발행국가
- 미국
- 분량
- 4 페이지
- ISSN
- P 2162-7541