3D Interconnect Process Integration and Characterization of Back Side Illuminated CMOS Image Sensor with 1.75 mu m Pixels

초록

The authors demonstrate process integration of a back side illuminated (BSI) 2 megapixel complementary metal oxide semiconductor (CMOS) sensor utilizing three-dimensional (3D) integration and wafer manufacturing operations with a silicon-on-insulator epi wafer. The manufacturing feasibility of a BSI CMOS image sensor is demonstrated and compared between the front side illuminated (FSI) and BSI versions of the sensor with the same fabrication process. The 3D integration processes are evaluated to obtain stable performance of the BSI CMOS image sensor. The broadband quantum efficiency (81% for BSI) is improved 2.7 times over FSI sensitivity. The dark current and other key pixel performance measures are compared against an equivalent conventional sensor. Simulations that predict the performance of a full-color sensor are discussed.

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