A 7-Bit 1.6 GS/s Hybrid Capacitive-to-Charge-Injection DAC-Based Flash-Assisted Time-Interleaved SAR ADC with Background Gain Calibration for Temperature Robustness

초록

This paper presents a 7-bit 1.6 GS/s hybrid capacitive-to-charge-injection DAC (C-CIDAC)-based flash-assisted time-interleaved (FATI) successive-approximation-register (SAR) analog-to-digital converter (ADC) that improves the limited input range and temperature-induced gain variation in conventional CIDAC-based SAR ADCs. In the proposed architecture, a DAC voltage common-mode (VCM) shift up to 48 LSBs is internally generated during the coarse conversion, enabling a rail-to-rail ADC input range while improving VCM independence. In addition, a fully on-chip background gain-calibration scheme is introduced to compensate for the gain error between the CDAC and CIDAC caused by temperature variation. By taking advantage of the pulse-activation-based CIDAC operation scheme, the proposed calibration achieves robust gain tracking without any external bias control. The proposed four-channel FATI-SAR ADC was designed using a 65 nm CMOS process and occupies 13,628 mu m2, including the background calibration circuitry. The peak differential nonlinearity (DNL) and integral nonlinearity (INL) are +0.60/-0.60 LSB and +0.72/-0.76 LSB at -40 degrees C and 105 degrees C, respectively. At Nyquist input, the simulated SNDR and SFDR are 41.52 dB and 53.36 dB, respectively. The ADC consumes 8.551 mW and achieves an FoMW of 54.6 fJ/conversion step. Comprehensive post-layout simulation results show that the proposed FATI-SAR ADC operates at 1.6 GS/s and maintains an ENOB above 6.3 across a temperature range from -40 degrees C to 105 degrees C at Nyquist input.

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