A Diacnosable Network-on-Chip for FPGA Verification of Intellectual Properties

초록

Editor's note: Debug and validation are important steps required to ensure that systems-on-chip satisfies the design specs. This article presents an elegant diagnosis technique integrated within the network-on-chip infrastructure. The authors demonstrate the proposed technique on an FPGA prototype.-Umit Y. Ogras, Arizona State University © 2013 IEEE.

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