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Background Injection-Pulse Duty Correction With 0.05% Accuracy for Dual-Edge ILPLL Using Sub-Sampling Charge Pump
- Yoon, Dong-Hyun;
- Kim, Tony Tae-Hyoung;
- Baek, Kwang-Hyun
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This paper proposes a background duty-cycle corrections (DCC) scheme for a dual-edge injection locking phase-locked loop. Dual-edge injection enhances noise performance by effectively doubling the injection ratio. However, noise and spurs are highly sensitive to the duty cycle distortion. The proposed DCC scheme senses the duty-cycle conventional duty correction technique directly senses the duty of the injection pulse. The proposed DCC scheme is implemented in a 65 nm CMOS process and achieves a duty error correction accuracy of 0.05% under 3-sigma mismatch conditions.
키워드
clocks; phase locked loops
- 제목
- Background Injection-Pulse Duty Correction With 0.05% Accuracy for Dual-Edge ILPLL Using Sub-Sampling Charge Pump
- 저자
- Yoon, Dong-Hyun; Kim, Tony Tae-Hyoung; Baek, Kwang-Hyun
- 발행일
- 2025-09
- 유형
- Article
- 권
- 61
- 호
- 1