Development and Applications of 3-Dimensional Integration Nanotechnologies

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초록

Unlike conventional two-dimensional (2D) planar structures, signal or power is supplied through through-silicon via (TSV) in three-dimensional (3D) integration technology to replace wires for binding the chip/wafer. TSVs have becomes an essential technology, as they satisfy Moore's law. This 3D integration technology enables system and sensor functions at a nanoscale via the implementation of a highly integrated nano-semiconductor as well as the fabrication of a single chip with multiple functions. Thus, this technology is considered to be a new area of development for the systemization of the nano-bio area. In this review paper, the basic technology required for such 3D integration is described and methods to measure the bonding strength in order to measure the void occurring during bonding are introduced. Currently, CMOS image sensors and memory chips associated with nanotechnology are being realized on the basis of 3D integration technology. In this paper, we intend to describe the applications of high-performance nano-biosensor technology currently under development and the direction of development of a high performance lab-on-a-chip (LOC).

키워드

3D Integration; Bonding Strength; CMOS Sensor; Biosensor; TSV; ON-A-CHIP; CMOS IMAGE SENSOR; HIGH-ASPECT-RATIO; RETINAL PROSTHESIS; 3D INTEGRATION; SILICON VIAS; SURFACE ACTIVATION; FLOATING-GATE; FLASH MEMORY; TECHNOLOGY
제목
Development and Applications of 3-Dimensional Integration Nanotechnologies
저자
Kim, Areum; Choi, Eunmi; Son, Hyungbin; Pyo, Sung Gyu
DOI
10.1166/jnn.2014.8758
발행일
2014-02
유형
Review
저널명
Journal of Nanoscience and Nanotechnology
권
14
호
2
페이지
2001 ~ 2011