A novel high performance junctionless FETs with saddle-gate

초록

In this paper, a novel junctionless field effect transistors (JL FETs) with a saddle-gate structure has been proposed, and the I-V characteristics has been extensively studied by TCAD device simulation. The performance comparison between saddle-gate JL FETs and conventional triple-gate JL FETs has also been performed. The influence of gate dielectric on device property has also been investigated. A scheme of design optimization of saddle-gate JL FETs has also been proposed.

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