영상 압축 응용분야를 위한 DCT 아키텍처 개발

초록

This paper presents an efficient architecture for 2n-point DCT algorithm. The proposed approach makes use of the fact that, in most DCT applications, the scaling operation in the DCT unit can be eliminated and combined with the scaling operation in the quantizer unit. This important property is efficiently exploited with the CORDIC (COordinate Rotation DIgital Computer) algorithm to produce a regular architecture suitable for VLSI implementation. Although there have been several attempts to exploit CORDIC algorithm in developing DCT architectures, the proposed approach provides the most efficient way for scaled DCT applications by completely eliminating the scale factor compensation.

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