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A Compact Dual-Mode SAR ADC With Mismatch Error Shaping Using Prediction-Error-Free 3-Level Analog Prediction and 1-bit Barrel-Shift Dithering
- Seong, Kiho;
- Seo, Jeetaeck;
- Lee, Jeonghun;
- Lee, Sukho;
- Kim, Tony Tae-Hyoung;
- ... Baek, Kwang-Hyun
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0초록
This paper presents a compact dual-mode successive-approximation-register (SAR) analog-to-digital converter (ADC) featuring mismatch error shaping (MES). To resolve the input dynamic range loss of conventional MES, a prediction-error-free 3-level analog prediction scheme is proposed. By adaptively bypassing predictions via comparator offsets, this scheme eliminates prediction errors and overcomes the input frequency limitations of conventional prediction methods. Furthermore, to extend the applicability of MES to Nyquist ADCs, a low-overhead 1-bit barrel-shift dithering technique is introduced to randomize capacitive digital-to-analog converter (CDAC) mismatches. Fabricated in a 65 nm CMOS process, the prototype occupies a core area of 0.01 mm(2) . In the noise-shaping (NS) mode, the ADC achieves a 78.5 dB signal-tonoise-and-distortion ratio (SNDR) and a 91.5 dB spurious-free dynamic range (SFDR) over a 31.25 kHz bandwidth, yielding a Schreier figure-of-merit (FoM(S)) of 175.8 dB. In the Nyquist mode, the 1-bit barrel-shift dithering-based MES improves the SFDR from 69.7 dB to 83.7 dB at the Nyquist input frequency.
키워드
- 제목
- A Compact Dual-Mode SAR ADC With Mismatch Error Shaping Using Prediction-Error-Free 3-Level Analog Prediction and 1-bit Barrel-Shift Dithering
- 저자
- Seong, Kiho; Seo, Jeetaeck; Lee, Jeonghun; Lee, Sukho; Kim, Tony Tae-Hyoung; Baek, Kwang-Hyun
- 발행일
- 2026-07
- 유형
- Article; Early Access
- 언어
- ENG
- 출판사
- IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
- 발행국가
- 미국
- ISSN
- E 1558-0806
P 1549-8328