An experimental load matching technique for RF CMOS power amplifier

초록

A load matching method for CMOS PA (power amplifier) design is proposed. The contours for RF power and efficiency call be drawn while considering external L and C as tunable X and Y variables. On the basis of the existence of this contour, the realization of load matching of CMOS PA is easily achieved and optimized. A tested CMOS PA based on 0.18 mu m CMOS technology shows a design example whose P1dB is 17.8 dBm and power efficiency 37%, respectively. (c) 2008 Wiley Periodicals, Inc.

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