두 배의 Rail-to-Rail 입력 범위를 갖는 NTV SAR ADC

초록

This paper presents a low-power 0.6-V 10-bit 200-kS/s double rail-to-rail successive approximation register (SAR)analog-to-digital converter (ADC). The proposed scheme allows input signal with 4 times power which is compared withconventional one by applying proposed rail-to-rail scheme, and that improves signal-to-noise ratio(SNR) of NTV SAR ADCs. The prototype was designed using 65-nm CMOS technology. At a 0.6-V supply and 2.4-Vpp(differential) and 200-kS/s, theADC achieves an SNDR of 59.87 dB and consumes 364.5-nW. The ADC core occupies an active area of only 84×100㎛^2.

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