Symmetric and Asymmetric Configuration of Parallel-Switched d-Type Multilevel Inverter

초록

Total harmonic distortion (THD) and voltage stress across the switches are critical issues in power electronic systems. Although multilevel inverters (MLIs) were initially used to minimize these issues, doing so is challenging when simultaneously attempting to minimize the number of components such as switches, dc sources, and gate drivers. To address this problem, a new pd-type MLI is presented with two back-to-back connected d-type modules with an H-bridge that generates the negative voltage levels. The proposed topology with ten unidirectional switches and four dc sources operates in symmetric and asymmetric configuration to generate 9, 13, and 17 voltage levels. The presented inverter is extended using cascaded connections to attain more output voltage levels, making it usable for the applications with diverse number of dc links for medium- and high-voltage applications. The proposed topology also exhibits small THD, low number of power electronic components, and low total voltage stress across the switches in each cycle. Furthermore, a widely used nearest level control (NLC) modulation technique is used to generate output voltage levels with a minimum amount of THD at the output. Finally, simulations were performed using MATLAB/Simulink and experiments were conducted to validate the performance of the proposed topology.

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