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4-bit 2-Gsample/s flash A/D converter using latched-skewed-logic in 0.13um CMOS
- Lee, J.H.;
- Kim, Y.J.;
- Kim, S.;
- Baek, K.H.
Citations
SCOPUS
1초록
4-bit 2-Gsample/s flash A/D converter is presented. It is realized in a digital 0.13um CMOS technology. To compensate for timing skew and delay problem at comparator outputs, a new latched-skewed-logic is introduced; the proposed latched-skewed-logic improves the performance of the A/D converter with negligible increase in power consumption. The simulation results show that the implemented A/D converter, operating with a sampling frequency of 2GHz, has an effective number of bits (ENOB) of 3.92 with an input frequency of 100MHz and 3.81 with a Nyquist input while consuming only 18mW. This corresponds to a figure-of-merit (FoM) of 0.6 pJ/convstep at Nyquist. The active area is 0.035mm2.
키워드
A/d converters; Active areas; Cmos technologies; Effective number of bits; Input frequencies; Nyquist; Power consumptions; Sampling frequencies; Simulation results; Timing skews; CMOS integrated circuits
- 제목
- 4-bit 2-Gsample/s flash A/D converter using latched-skewed-logic in 0.13um CMOS
- 저자
- Lee, J.H.; Kim, Y.J.; Kim, S.; Baek, K.H.
- 발행일
- 2008-09
- 유형
- Conference Paper
- 저널명
- Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2008
- 페이지
- 267 ~ 270
- 언어
- ENG
- 분량
- 4 페이지
- ISSN
- P 0000-0000