K-means Clustering-specific Lightweight RISC-V processor

Lee, W.; Park, J.; Byun, C.; Choi, E.; Lee, J.-H.; Lee, W.; Byun, K.J.; Han, K.

doi:10.1109/ISOCC53507.2021.9613863

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K-means Clustering-specific Lightweight RISC-V processor

Lee, W.;
Park, J.;
Byun, C.;
Choi, E.;
Lee, J.-H.;
... Lee, W.;
외 2명

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초록

While the demand for edge devices performing K-means clustering algorithm is expected to explode, this paper introduces a K-means clustering-specific processor for edge devices. The processor consists of hardware to accelerate the K-means algorithm and lightweight RISC-V core, and functional validation has been completed through RTL simulation and FPGA prototyping. The processor prototype demonstrates its excellence by performing the K-means algorithm about 56 times faster. © 2021 IEEE.

키워드

acclerator; K-means clustering; RISC-V processor

제목: K-means Clustering-specific Lightweight RISC-V processor

저자: Lee, W.; Park, J.; Byun, C.; Choi, E.; Lee, J.-H.; Lee, W.; Byun, K.J.; Han, K.

DOI: 10.1109/ISOCC53507.2021.9613863

발행일: 2021-10

유형: Proceedings Paper

저널명: Proceedings - International SoC Design Conference 2021, ISOCC 2021

페이지: 391 ~ 392

언어: ENG

출판사: Institute of Electrical and Electronics Engineers Inc.

분량: 2 페이지

ISSN: P 0000-0000