Effect of Source and Drain Contacts Schottky Barrier on 3C-SiC Nanowire FETs I-V Characteristics

초록

In this work, SiC nanowire (NW) FETs are prepared and their electrical measurements are presented. From the samples fabricated on the same substrate. various I-Vs shapes are obtained (linear, non linear symmetric, and asymmetric). With the assistance Of simulation, we show that this is a result of different values of Schottky Barrier Heights (SBH) at Source (S) / Drain (D) contacts of FETs. An origin for this might be a non uniformity in annealing, NW doping level and high interface traps density (that pins the Fermi level) as well as the high sensitivity of the metal-NW contacts to local surface contaminations.

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