A 5.4 mW concurrent low noise CMOS LNA for L1/L5 GPS application

초록

In this paper, a concurrent CMOS LNA for GPS application is presented, which supports L1 and L5 only modes as well as L1 and L5 simultaneous mode. To achieve concurrent operation, new cascode configuration employing a single common-source input stage and two common-gate output stages is proposed. And the band-pass matching technique using two capacitor banks is applied to achieve gain and output return loss tunability. It is implemented using 0.13 mu m CMOS technology. The LNA achieved low noise figures of 1.68 and 1.67 dB with high gains of 15.7 dB and 16.7 dB at L1 and L5 band, respectively and showed more than 10 dB input and output return losses. The LNA chip consumes low current of 4.5 mA from 1.2 V supply.

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