Low-power pipelined phase accumulator using CMOS-CML hybrid F/Fs for pre-skewing operation

초록

In this paper, a low-power pipelined phase accumulator (PACC) for high-speed direct digital frequency synthesizers (DDFSs) is presented. In the proposed PACC structure, the accumulator core block and the post-skewing block are based on current mode logic (CML) design topology for high-speed operations, whereas the pre-skewing block consists of static CMOS D-F/Fs and CMOS-CML hybrid F/Fs for low-power operations. The proposed CMOS-CML hybrid F/F provides fast level conversion (CMOS to CML) by having separate current sources and it also consumes low power dissipation by sequentially activating the current sources. Simulated results show that the proposed 24-bit PACC reduces power consumption by 31% compared with a conventional pipelined architecture when input data is updated every eight clock cycles. The operating speed of the proposed PACC is 45% faster than that of the conventional pipelined PACC under the condition of the same power dissipation.

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