디지털 주파수 보정과 지터 제거 기법을 적용한 2.5 Gb/s 버스트 모드 클럭 데이터 복원기

초록

In this paper, 2.5 Gb/s burst-mode clock and data recovery(CDR) is presented. Digital frequency calibration scheme isadopted to eliminate mismatch between the input data rate and the output frequency of the gated voltage controlledoscillator(GVCO) in the clock recovery circuitry. A jitter rejection scheme is also used to reduce jitter caused by inputdata. The proposed burst-mode CDR is designed using 0.11 μm CMOS technology. Post-layout simulations show thatpeak-to-peak jitter of the recovered data is 14 ps with 0.1 UI input referred jitter, and maximum tolerance of consecutiveidentical digit(CID) is 2976 bits without input data jitter. The active area occupies 0.125 mm2 without loop filter and thetotal power consumption is 94.5 mW.

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