ScholarWorks@중앙대학교

초록

This paper presents a novel high-precision 11-bit single-slope/successive approximation register analog-to-digital converter (SS/SAR ADC) architecture specifically designed for CMOS image sensors (CISs). The proposed design solves critical challenges in conventional ADCs by utilizing only two reference voltages, thereby minimizing voltage mismatch and completely eliminating the need for complex switch arrays. This unique approach reduces the transistor count by 64 per column ADC, significantly enhancing area efficiency and circuit simplicity. Furthermore, a groundbreaking on-chip fine step range calibration technique is introduced to mitigate the impact of parasitic capacitance, ensuring the precise alignment between coarse and fine steps and achieving exceptional linearity. Fabricated using a 0.18-mu m CMOS process, the ADC demonstrates superior performance metrics, including a differential nonlinearity (DNL) of -1/+1.86 LSB, an integral nonlinearity (INL) of -2.74/+2.79 LSB, an effective number of bits (ENOB) of 8.3 bits, and a signal-to-noise and distortion ratio (SNDR) of 51.77 dB. Operating at 240 kS/s with a power consumption of 22.16 mu W, the ADC achieves an outstanding figure-of-merit (FOMW) of 0.291 pJ/step. These results demonstrate the proposed architecture's potential as a transformative solution for high-speed, energy-efficient CIS applications.

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