A Calibration-Free Fractional-N PLL with a Time-Averaged Current DAC for High Linearity

초록

This paper proposes a calibration-free Type-II fractional-N PLL that achieves high linearity by employing a time-averaged current DAC. By adopting a time-averaged current DAC, the proposed architecture inherently enables calibration-free operation and achieves superior linearity, successfully overcoming the fundamental limitations of conventional DTC- and PI-based approaches. The proposed time-averaged current DAC consists of two cells and a variable pulse-width generator. Interpolation is achieved by controlling the injection time of the cells’ output currents, effectively performing time-averaging between two current levels. By performing interpolation in the time domain instead of using conventional analog DAC implementations, the proposed approach simplifies the design and achieves improved linearity. The combination of the 3-bit time-averaged current DAC and the quad-phase divider reduces the quantization noise by 24 dB. The proposed PLL is designed in a 65 nm process. Simulation results show that it consumes 3.41 mW of power with a 25 MHz reference frequency and achieves an RMS jitter of 231.8 fs, integrated from 1 kHz to 100 MHz, and a figure-of-merit () of −267.1 dB.

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