백광현

전체 125건 중 31번부터 40번까지의 결과를 표시합니다.

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A 0.5 V 10 b 3 MS/s 2-Then-1b/Cycle SAR ADC With Digital-Based Time-Domain Reference and Dual-Mode Comparator

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Noise Immunity-Enhanced Capacitance Readout Circuit for Human Interaction Detection in Human Body Communication Systems

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Energy Efficient Distance Computing: Application to K-Means Clustering

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SIMO DC‐DC Converter with Low‐Complexity Hybrid Comparator‐Charge Control

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A Switched-Capacitor DC-DC Converter with Conversion Ratio Controller for Wide Output Power Range

2021

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A 3.2 GHz 178fsrmsJitter Injection Locked Clock Multiplier Using Sub-Sampling FTL and DLL for In-Band Noise Improvement

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A SAR ADC with Segment Binary Weighted Attenuation Capacitor DAC layout technique

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A reference-sampling based calibration-free fractional-N PLL with A PI-linked sampling clock generator

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A 0.007 mm 0.6 V 6 MS/s Low-Power Double Rail-to-Rail SAR ADC in 65-nm CMOS

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A 0.5 V 10 b 3 MS/s 2-Then-1b/Cycle SAR ADC With Digital-Based Time-Domain Reference and Dual-Mode Comparator

Noise Immunity-Enhanced Capacitance Readout Circuit for Human Interaction Detection in Human Body Communication Systems

Energy Efficient Distance Computing: Application to K-Means Clustering

SIMO DC‐DC Converter with Low‐Complexity Hybrid Comparator‐Charge Control

A Switched-Capacitor DC-DC Converter with Conversion Ratio Controller for Wide Output Power Range

A 3.2 GHz 178fsrmsJitter Injection Locked Clock Multiplier Using Sub-Sampling FTL and DLL for In-Band Noise Improvement

A SAR ADC with Segment Binary Weighted Attenuation Capacitor DAC layout technique

A reference-sampling based calibration-free fractional-N PLL with A PI-linked sampling clock generator

A 0.007 mm 0.6 V 6 MS/s Low-Power Double Rail-to-Rail SAR ADC in 65-nm CMOS

A 2.4 GHz Fractional-N Sub-Sampling PLL with a Hybrid Type Phase-Interpolator